1. Field of the Invention
The present invention relates to imaging systems. More specifically, the present invention relates to threshold architecture for ladar systems.
2. Description of the Related Art
A ladar (Laser Detecting and Ranging) system is an electro-optical system for object detection and ranging using a laser as an illuminator and a receiver which detects the return (reflection) of the laser from an object or target and converts the time of the return to range. This is done over two dimensions for a three dimensional range map. Up to now, most ladar systems have been of the scanning variety and are referred to as scanning ladar systems. In this type of ladar, a laser is pulsed at a high rate with one pulse per pixel (image element) or portion of the target area to be studied. The laser is scanned such that each pixel in the field of view is illuminated and detected. Each laser pulse may be reflected from the target area and received by a detector at the ladar site. The detector includes a signal processor to determine when the detector signal is noise and when a reflected laser pulse (return) has been detected. This can be accomplished by setting a threshold level such that anything below the threshold is considered noise and anything above it is considered a return. The detector and the laser are scanned congruently so that the detector is positioned to receive any reflected laser beams from the most recent laser pulse. After the entire target area has been scanned, the ladar system has enough information to determine the approximate range to any object within the target area and the approximate shape of any detected object.
Scannerless ladar, or flash ladar, is the next big step in radar technology. A flash ladar system illuminates the entire object plane with a single, large pulse from the laser. This laser pulse is then reflected from any object within the target area. The reflected laser pulse is received by a focal plane array (FPA), a two dimensional array of several detectors placed in the focal plane of the receiver optics. Flash ladar has the potential to dramatically increase the image frame rate over scanning systems while eliminating bulky and expensive mechanical moving parts.
One problem with flash ladar has to do with the need to compensate for variations in detector gain, noise, and atmospheric feedback. There is no guarantee that every detector on the array is going to be exactly the same. In fact, it is more likely that each detector will have a slightly different gain and bias. Some areas of the array may be more noisy than others, resulting in varying noise levels. This problem is particularly prevalent with advanced detector arrays such as the APD (avalanche photo diode). Individual bias adjustment of each detector in the array is required to provide detector-to-detector gain uniformity and to optimize the signal to noise performance for the detector.
Handling bias adjustment internally in the detector signal processor requires more complex signal processing than current detector readout electronics can handle. Readout electronics have been limited to simple signal processing due to the requirement of maintaining signal processing circuitry inside the unit cell. The alternative is to have an individual control line to each cell, but this becomes a problem for large arrays. In an FPA with 3000 cells, each control line translates to 3000 connections. A key to having an integrated signal processor unit cell is to have flexibility without having many individual control lines.
Hence, a need exists in the art for an efficient system and method for individual bias adjustment of detectors in a large ladar focal plane array.
The need in the art is addressed by the present invention, which provides an integrated detector and signal processor for ladar focal plane arrays which internally compensates for variations in detector gain, noise, and aerosol backscatter. The invention is comprised of a detector element for receiving an input signal and a circuit for generating a threshold based on the RMS noise level of the input signal and determining when the input signal is above that threshold. The detector element is physically located in the interior of the detector array, while the signal processing circuitry is located on the periphery of the array. In the preferred embodiment, the signal processor also includes a circuit for sampling the input signal and storing multiple samples, allowing for multiple returns to be detected. In the preferred embodiment, the signal processor can be operated in two modes: self triggered and externally triggered (range-gate mode). In the self triggered mode, the detector continually monitors and samples the incoming signal until a return is detected (by the thresholding circuit). In the range-gate mode, the detector stops sampling when it receives a signal from an external source. Once the data has been acquired, readout electronics output the stored samples along with the stored xe2x80x9cstoppedxe2x80x9d time code to an external computer.